Referring to FIGS. 6, 7, 8, and 9, a conventional asynchronous communication circuit will be described below.
FIG. 6 is a conceptual illustration for explaining communications between typical asynchronous communication circuits. For example, such asynchronous communication circuits are used for communications between the outdoor unit and the indoor unit of an air conditioner. FIG. 7 is a structural diagram showing the conventional asynchronous communication circuit. FIG. 8 is a signal waveform chart showing an operation of the conventional asynchronous communication circuit. FIG. 9 is a signal waveform chart showing an operation performed when the conventional asynchronous communication circuit has a large duty ratio.
In FIG. 6, transmit data is outputted from a transmitting terminal TXD of an asynchronous communication circuit U1 of an outdoor unit and is received by a receiving terminal RXD of an asynchronous communication circuit U2 of an indoor unit through an insulating component Z2. Further, transmit data is outputted from a transmitting terminal TXD of the asynchronous communication circuit U2 of the indoor unit and is received by the receiving terminal RXD of the asynchronous communication circuit U2 of the indoor unit through an insulating component Z1. Such communications are carried out at a predetermined data rate.
Referring to FIGS. 7 and 8, an operation of the conventional asynchronous communication circuit will be described below.
In FIG. 7, the conventional asynchronous communication circuit is constituted of a divider counter 3 for dividing a clock outputted from a clock generator circuit 1 while using, as a reset signal, a start bit decision signal outputted from a start bit decision circuit 2, a data transmission shift register 7 which uses, as a data transmission shift clock, a clock outputted from the divider counter 3, and a data reception shift register 6 which uses, as a data reception shift clock, a clock outputted from the divider counter 3.
When data is received, data S102 transmitted from the transmitting terminal TXD of the asynchronous communication circuit U2 has a waveform 91 shown in FIG. 8. In FIG. 8, the transmit data represents “10101010.” When the serial data passes through the insulating component Z1, a fall delay t1 and a rise delay t2 are added to output data S103 due to the characteristics of the insulating component Z1, and the “H” period and “L” period of the waveform are changed with a varied duty ratio as indicated by 92 of FIG. 8. In receive data inputted to the receiving terminal RXD of the asynchronous communication circuit U1, a start bit is decided by the start bit decision circuit 2 and a start bit decision signal is outputted from the start bit decision circuit 2. The divider counter 3 reset by the start bit decision signal starts dividing a clock signal outputted from the clock generator circuit 1 and outputs data S200 as a data reception shift clock indicated by 93 of FIG. 8. The clock enables data to be acquired at the center of the data S102 having been received according to a predetermined communication speed. The data S103 is received by the data reception shift register 6 according to the clock. In this case, 8-bit reception is carried out and thus the data is stored in the data reception shift register while the reception shift clock is outputted eight times like data S300 indicated as a waveform 94. Thereafter, the data is outputted to an internal circuit and the reception is completed.
When data is transmitted, a clock signal from the clock generator circuit 1 that is defined by a predetermined communication speed is divided by the divider counter 3, and transmit data S100 is transmitted from the data transmission shift register 7 with the divided clock serving as data S200 of the data transmission shift clock indicated as a waveform 95 in FIG. 8. This serial data is transmitted from the transmitting terminal TXD of the asynchronous communication circuit U1 with a waveform 96 of FIG. 8 and is inputted to the insulating component Z2. The fall delay t1 and the rise delay t2 are added as in the reception and data S101 is outputted. The data S101 reaches the receiving terminal RXD of the asynchronous communication circuit U1 with a waveform deformed like a waveform 97 of FIG. 8. The receiving operation of the asynchronous communication circuit U2 is similar to that of the asynchronous communication circuit U1.
Further, the following example is also available: a send/receive clock is automatically set by data in a predetermined format at the start of communications and the changing points of receive data are sampled, so that a receive clock is automatically corrected (patent document 1).
However, in the transmission and reception, the insulating components Z1 and Z2 between the asynchronous communication circuits U2 and U1 are typically different in the rise time t2 and the fall time t1 on a signal waveform. When a delay due to the rise time and the fall time is sufficiently smaller than a communication speed, communications can be carried out by the conventional a synchronous communication circuit with no problem. However, when the communication speed increases, a waveform with a largely varied duty ratio in High period and Low period is inputted to the receiving terminal, like a waveform 102 of FIG. 9. Further, data cannot be accurately received by a waveform 103 indicated as the data receiving shift clock S200 in FIG. 9. Thus, when components with a large difference in rise delay and fall delay have to be inserted in a communication system, a communication speed has to be sufficiently low relative to the difference in delay.